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1 ? fn6441.0 ISL8009 1.5a low quiescent current 1.6mhz high efficiency synchronous buck regulator ISL8009 is an integrated powe r controller rate for 1.5a, 1.6mhz step-down regulator that is ideal for any low power, low-voltage applications. it is optimized for generating low output voltages down to 0.8v. the supply voltage range is from 2.7v to 5.5v, allowing for the use of a single li+ cell, three nimh cells or a regulated 5v input. it has a guaranteed minimum output current of 1.5a. 1.6mhz pulse-width modulation (pwm) switching frequency allows for using small external components. it has flexible operation mode selection of forced pwm mode and pfm mode with as low as 17a quiescent current for highest light load efficiency to maximize battery life. the ISL8009 includes a pair of low on-resistance p-channel and n-channel internal mosfets to maximize efficiency and minimize external co mponent count. duty-cycle operation allows less than 400mv dropout voltage at 1.5a. the ISL8009 offers a 200ms power-on-reset (por) timer at power-up. the timer output can be reset by rsi. when shutdown, ISL8009 discharges the output capacitor through a 100 resistor. other features include internal digital soft- start, enable for power sequenc e, overcurrent protection, and thermal shutdown. the ISL8009 is offered in a 2mmx3mm 8 ld dfn package with 1mm maximum height. the complete converter occupies less than 1cm 2 area. features ? high efficiency synchronous buck regulator with up to 95% efficiency ? 200ms reset timer ? 2.7v to 5.5v supply voltage ? 3% output accuracy ov er-temperature/load/line ? 1.5a guaranteed output current ? 17a quiescent supply current in pfm mode ? selectable forced pwm mode and pfm mode ? less than 1a logic controlled shutdown current ? 90% maximum duty cycle for lowest dropout at 1.5a ? internal current mode compensation ? internal digital soft-start ? peak current limiting, short circuit protection ? over-temperat ure protection ? enable ? soft discharge disable ? small 8 ld 2mmx3mm dfn ? pb-free plus anneal available (rohs compliant) applications ? dc/dc pol modules ? c/p, fpga and dsp power ? plug-in dc/dc modules for routers and switchers ? portable instruments ? test and measurement systems pinout ISL8009 (8 ld dfn) top view ordering information part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL8009irz-t 009 -40 to +85 8 ld 2x3 dfn l8.2x3 note: intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-f ree peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 2 3 4 1 7 6 5 8 vin en por skip lx gnd vfb rsi data sheet july 11, 2007 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2007. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn6441.0 july 11, 2007 absolute maximum ratings (reference to gnd) thermal information supply voltage (v in ) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v en, rsi, skip, vfb, por . . . . . . . . . . . . . . . . . -0.3v to vin + 0.3v lx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5v to 6.5v vfb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 2.7v recommended operating conditions vin supply voltage range . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v load current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0a to 1.5a ambient temperature range . . . . . . . . . . . . . . . . . . .-40c to +85c thermal resistance (typical, notes 1, 2) ja (c/w) jc (c/w) 2x3 dfn package . . . . . . . . . . . . . . +78 +11 junction temperature range. . . . . . . . . . . . . . . . . .-55c to +125c storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured in free air with the component mounted on a high e ffective thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379. 2. jc , ?case temperature? location is at the center of the exposed metal pad on the package underside. see tech brief tb379. electrical specifications unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and the typical specification are measured at the following conditions: t a = +25c, en = vin, rsi = skip = 0v, v in = 5v, l = 2.2h, c1 = c2 = 20f, i out = 0a to 1.5a, unless otherwise noted. see ?typical applications? on page 8. parameter symbol test conditions min typ max units input supply vin undervoltage lockout threshold v uvlo rising - 2.5 2.7 v falling 2.2 2.4 - v quiescent supply current i vin skip = vin, no load at the output - 17 30 a skip = vin, no load at the output and no switches switching, design info only -15-a skip = gnd, no load at the output - 3.7 6 ma shutdown supply current i sd v in = 5.5v, en = low - 0.1 2 a output regulation vfb regulation voltage v vfb 0.784 0.8 0.816 v vfb bias current i vfb vfb = 0.75v - 0.1 - a output voltage accuracy v in = v o + 0.5v to 5.5v, i o = 0a to 1a -3 - 3 % line regulation v in = v o + 0.5v to 5.5v (minimal 2.7v) - 0.2 - %/v compensation error amplifier trans-conduct ance adjustable version, design info only - 20 - a/v lx p-channel mosfet on-resistance v in = 5.5v, i o = 200ma - 0.12 0.22 v in = 2.7v, i o = 200ma - 0.16 0.27 n-channel mosfet on-resistance v in = 5.5v, i o = 200ma - 0.11 0.22 v in = 2.7v, i o = 200ma - 0.15 0.27 p-channel mosfet peak current limit i pk 1.8 2.1 2.4 a lx maximum duty cycle i o = 1.5a 90 - % pwm switching frequency f s 1.35 1.6 1.75 mhz lx minimum on time skip = low (forced pwm mode) 70 100 ns soft-start-up time -1.1- ms soft-discharge resistor enable = 0 80 100 120 ISL8009
3 fn6441.0 july 11, 2007 pin descriptions vin input supply voltage. connect a 10f ceramic capacitor to power ground. en regulator enable pin. enable t he output when driven to high. shutdown the chip and discharge output capacitor when driven to low. do not leave this pin floating. por 200ms timer output. at power-up or en hi, this output is a 200ms delayed power-good signal for the output voltage. this output can be reset by a low rsi signal. 200ms starts when rsi goes to high. skip mode selection pin. connect to logic high or input voltage vin for pfm mode; connect to logic low or ground for forced pwm mode. do not leave this pin floating. lx switching node connection. connect to one terminal of inductor. gnd system ground. vfb buck regulator output feedback. connect to the output through a resistor divider for adjustable output voltage (ISL8009-adj). for preset output voltage, co nnect this pin to the output. rsi this input resets the 200ms timer. when the output voltage is within the pgood window, an in ternal timer is started and generates a por signal 200ms later when rsi is low. a high rsi resets por and rsi high to low transition restarts the internal counter if the output voltage is within the window, otherwise the counter is reset by the output voltage condition. exposed pad the exposed pad must be connect ed to the gnd pin for proper electrical performance. the exposed pad must also be connected to as much as possible for optimal thermal performance. por output low voltage sinking 1ma, vfb = 0.7v - - 0.3 v delay time 150 200 275 ms por pin leakage current por = vin = 3.6v - 0.01 0.1 a minimum supply voltage for valid por signal 1.2 - - v internal pgood low rising threshold percent age of nominal regulation voltage 89.5 92 94.5 % internal pgood low falling threshold percent age of nominal regulation voltage 85 88 91 % internal pgood high rising threshold percentage of nominal regulation voltage 108 112 114 % internal pgood high falling threshold perc entage of nominal regulation voltage 104 107 110 % internal pgood delay time -50- s en, skip, rsi logic input low --0.4v logic input high 1.4 - - v logic input leakage current pulled up to 5.5v - 0.1 1 a thermal shutdown - 160 - c thermal shutdown hysteresis -25-c electrical specifications unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and the typical specification are measured at the following conditions: t a = +25c, en = vin, rsi = skip = 0v, v in = 5v, l = 2.2h, c1 = c2 = 20f, i out = 0a to 1.5a, unless otherwise noted. see ?typical applications? on page 8. (continued) parameter symbol test conditions min typ max units ISL8009
4 fn6441.0 july 11, 2007 typical operating performance (unless otherwise noted, operating conditions are: t a = +25c, v vin = 5v, en = vin, rsi = skip = 0v, l = 2.2h, c1 = 20f, c2 = 20f, i out = 0a) figure 1. efficiency vs load, v in = 3.3v pwm figure 2. efficiency vs load, v in = 3.3v pfm figure 3. efficiency vs load, v in = 5v pwm figure 4. efficiency vs load, v in = 5v pfm figure 5. v out regulation vs load, v out = 1.2v figure 6. v out regulation vs load, v out = 1.5v 0 10 20 30 40 50 60 70 80 90 100 0.00 0.25 0.50 0.75 1.00 1.25 1.50 output load (a) efficiency (%) 1.5v out - pwm 1.2v out - pwm 1.8v out - pwm 2.5v out - pwm 40 50 60 70 80 90 100 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.5 0 output load (a) efficiency (%) 1.5v out - pfm 1.2v out - pfm 1.8v out - pfm 2.5v out - pfm 0 10 20 30 40 50 60 70 80 90 100 0.00 0.25 0.50 0.75 1.00 1.25 1.50 output load (a) efficiency (%) 1.5v out - pwm 1.2v out - pwm 1.8v out - pwm 2.5v out - pwm 3.3v out - pwm 40 50 60 70 80 90 100 0.05 0.15 0.25 0.35 0.45 0.55 0.65 0.75 output load (a) efficiency (%) 1.5v out - pfm 1.2v out - pfm 1.8v out - pfm 2.5v out - pfm 3.3v out - pfm 1.10 1.12 1.14 1.16 1.18 1.20 1.22 1.24 1.26 1.28 1.30 0.00 0.25 0.50 0.75 1.00 1.25 1.5 0 output load (a) output voltage (v) 3.3v in - pwm 2.8v in - pwm 5v in - pwm 2.8v in - pfm 3.3v in - pfm 5v in - pfm 1.46 1.48 1.50 1.52 1.54 1.56 0.00 0.25 0.50 0.75 1.00 1.25 1.50 output load (a) output voltage (v) 3.3v in - pwm 2.8v in - pwm 2.8v in - pfm 3.3v in - pfm 5v in - pfm 5v in - pwm ISL8009
5 fn6441.0 july 11, 2007 figure 7. v out regulation vs load, v out = 1.8v figure 8. v out regulation vs load, v out = 2.5v figure 9. v out regulation vs load, v out = 3.3v figure 10. power dissipation vs load, v out = 1.2v figure 11. power dissipation vs load, v out = 1.5v figure 12. power dissipation vs load, v out = 1.8v typical operating performance (unless otherwise noted, operating conditions are: t a = +25c, v vin = 5v, en = vin, rsi = skip = 0v, l = 2.2h, c1 = 20f, c2 = 20f, i out = 0a) (continued) 1.77 1.78 1.79 1.80 1.81 1.82 1.83 1.84 1.85 1.86 0.00 0.25 0.50 0.75 1.00 1.25 1.50 output load (a) output voltage (v) 3.3v in - pwm 2.8v in - pwm 2.8v in - pfm 3.3v in - pfm 5v in - pfm 5v in - pwm 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 0.00 0.25 0.50 0.75 1.00 1.25 1.50 output load (a) output voltage (v) 3.3v in - pwm 3.3v in - pfm 5v in - pfm 5v in - pwm 3.27 3.29 3.31 3.33 3.35 3.37 3.39 0.00 0.25 0.50 0.75 1.00 1.25 1.50 output load (a) output voltage (v) 4v in - pwm 4v in - pfm 5.5v in - pwm 5v in - pfm 5v in - pwm 5.5v in - pfm 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.00 0.25 0.50 0.75 1.00 1.25 1.50 output load (a) power dissipation (w) 3.3v in - pwm 2.8v in - pwm 2.8v in - pfm 5v in - pwm 5v in - pfm 3.3v in - pfm 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.00 0.25 0.50 0.75 1.00 1.25 1.50 output load (a) power dissipation (w) 2.8v in - pwm 2.8v in - pfm 5v in - pwm 5v in - pfm 3.3v in - pfm 3.3v in - pwm 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.00 0.25 0.50 0.75 1.00 1.25 1.50 output load (a) power dissipation (w) 2.8v in - pwm 2.8v in - pfm 5v in - pwm 5v in - pfm 3.3v in - pfm 3.3v in - pwm ISL8009
6 fn6441.0 july 11, 2007 figure 13. power dissipation vs load, v out = 2.5v figure 14. power dissipation vs load, v out = 3.3v figure 15. power dissipation vs v in at no load, v out = 1.8v figure 16. output voltage regulation vs v in pwm mode figure 17. output voltage regulation vs v in skip mode figure 18. steady state operation at no load (pwm) typical operating performance (unless otherwise noted, operating conditions are: t a = +25c, v vin = 5v, en = vin, rsi = skip = 0v, l = 2.2h, c1 = 20f, c2 = 20f, i out = 0a) (continued) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.00 0.25 0.50 0.75 1.00 1.25 1.50 output load (a) power dissipation (w) 2.8v in - pwm 2.8v in - pfm 5v in - pwm 5v in - pfm 3.3v in - pfm 3.3v in - pwm 3.3v in - pfm 0 0.1 0.2 0.3 0.4 0.5 0.6 0.00 0.25 0.50 0.75 1.00 1.25 1.50 output load (a) power dissipation (w) 4v in - pfm 5.5v in - pwm 5v in - pfm 5v in - pwm 5.5v in - pfm 4v in - pwm 0 5 10 15 20 25 30 35 40 45 2.75 3.25 3.75 4.25 4.75 5.25 v in (v) power dissipation (mw) no load- pwm no load - pfm 0.0 0.5 1.0 1.5 2.0 2.5 2.02.53.03.54.04.55.05.5 input voltage (v) output voltage (v) 0.75a load 1.5a load no load -0.5 0.0 0.5 1.0 1.5 2.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 input voltage (v) output voltage (v) 0.75a load 1.5a load no load i l 0.2a/div v out ripple 20mv/div lx 2v/div ISL8009
7 fn6441.0 july 11, 2007 ISL8009 figure 19. steady state operation at no load (pfm ) figure 20. steady state operation with full load figure 21. load transient (pwm) f igure 22. load transient (pfm) figure 23. soft-start at no load figure 24. soft-start with pre-biased 1v typical operating performance (unless otherwise noted, operating conditions are: t a = +25c, v vin = 5v, en = vin, rsi = skip = 0v, l = 2.2h, c1 = 20f, c2 = 20f, i out = 0a) (continued) i l 0.2a/div v out ripple 20mv/div lx 2v/div i l 0.5a/div v out ripple 20mv/div lx 2v/div i l 1a/div v out ripple 50mv/div lx 2v/div i l 1a/div v out ripple 50mv/div lx 2v/div i l 1a/div v out 1v/div en 2v/div por 2v/div i l 1a/div en 2v/div v out 0.5v/div 1v pre-biased
8 fn6441.0 july 11, 2007 typical applications figure 25. soft-start at full load figure 26. soft-start at full load (zoom out) figure 27. output short circuit fig ure 28. output short circuit recovery typical operating performance (unless otherwise noted, operating conditions are: t a = +25c, v vin = 5v, en = vin, rsi = skip = 0v, l = 2.2h, c1 = 20f, c2 = 20f, i out = 0a) (continued) i l 1a/div v out 0.5v/div en 2v/div i l 1a/div v out 1v/div en 2v/div por 1v/div i l 1a/div v out 1v/div lx 2v/div i l 1a/div v out 1v/div figure 29. typical application diagram l lx gnd vfb rsi vin en por skip input 2.7v to 5.5v output 1.8v to 1.5a c 1 20f r 1 100k ISL8009 c 2 r 2 124k r 3 100k 2.2h 20f ISL8009
9 fn6441.0 july 11, 2007 block diagram theory of operation the ISL8009 is a step-down switching regulator optimized for battery-powered handheld applications. the regulator operates at 1.6mhz fixed switching frequency under heavy load condition to allow small external inductor and capacitors to be used for minimal printed-circuit board (pcb) area. at light load, the regulator reduces the switching frequency, unless forced to the fixed frequency to minimize the switching loss and to maximi ze the battery life. the quiescent current w hen the output is not loaded is typically only 17a. the supply current is typically only 0.1a when the regulator is shutdown. pwm control scheme the ISL8009 employes the current-mode pulse-width modulation (pwm) control sc heme for fast transient response and pulse-by-pulse current limiting. figure 30 shows the block diagram. the current loop consists of the oscillator, the pwm comparator comp, the current sensing circuit, and the slope compensation for the current loop stability. the current sensing circuit consists of the resistance of the p-channel mosfet when it is turned on and the current sense amplifier csa. the gain for the current sensing circuit is typically 0.4v/a. the control reference for the current l oops comes from the error amplifier eamp of the voltage loop. the pwm operation is initialized by the clock from the oscillator. the p-channel mosfet is turned on at the beginning of a pwm cycle and the current in the mosfet starts to ramp up. when the sum of the current amplifier csa and the compensation slope (0.675v/s) reach the control reference of the current loop , the pwm comparator comp sends a signal to the pwm logic to turn off the p-mosfet and to turn on the n-channel mosfet. the n-mosfet stays on until the end of the pwm cycle. figure 31 shows the typical operating waveforms during the pwm operation. the dotted lines illustrate the sum of the compensation ramp and the current-sense amplifier csa output. the output voltage is regulated by controlling the reference voltage to the current loop. the bandgap circuit outputs a 0.8v reference voltage to the voltage control loop. the feedback signal comes from the vfb pin. the soft-start figure 30. functional block diagram lx + + csa1 + + ocp 0.85v 0.17v skip + + + slop e comp slope comp 0.8v eamp comp pwm/pfm logic controller protection driver vfb + 0.736v 0.864v por skip shutdown vin gnd oscillator zero - cross sensing + bandgap scp + 0.2v en shutdown 200ms delay rsi 3pf 30pf 300k soft- start ISL8009
10 fn6441.0 july 11, 2007 block only affects the operation during the start-up and will be discussed separately. the error amplifier is a transconductance amplifier that converts the voltage error signal to a current output. the voltage loop is internally compensated with the 30pf and 300k rc network. the maximum eamp voltage output is precisely clamped to the bandgap voltage (1.172v). skip mode the ISL8009 enters a pulse-skipping mode at light load to minimize the switching loss by reducing the switching frequency. figure 32 illustrates the skip-mode operation. a zero-cross sensing circuit shown in figure 30 monitors the n-mosfet current for zero crossing. when 8 consecutive cycles of the n-mosfet crossi ng zero are detected, the regulator enters the skip mode. during the 8 detecting cycles, the current in the inductor is allowed to become negative. the counter is reset to zero when the current in any cycle does not cross zero. once the skip mode is entered, the pulse modulation starts being controlled by the skip comparator shown in figure 30. each pulse cycle is still synchro nized by the pwm clock. the p-mosfet is turned on at the clock and turned off when its current reaches 20% of the curr ent limit value (0.2v at the csa output). as the average inductor current in each cycle is higher than the average curr ent of the load, the output voltage rises cycle over cycle. when the output voltage reaches 1.5% above the nominal voltage, the p-mosfet is turned off immediately and the inductor current is fully discharged to zero and stays at zero. the output voltage reduces gradually due to the load current discharging the output capacitor. when the output voltage drops to the nominal voltage, the p-mosfet will be turned on again at the clock, repeating the previous operations. the regulator resumes normal pwm mode operation when the output voltage drops 1.5% below the nominal voltage. mode control the ISL8009 has a skip pin t hat controls the operation mode. when the skip pin is driven to low or shorted to ground, the regulator operates in a forced pwm mode. the forced pwm mode remains the fixed pwm frequency at light load instead of entering the skip mode. overcurrent protection the overcurrent protection is realized by monitoring the csa output with the ocp comparator, as shown in figure 30. the current sensing circuit has a gain of 0.4v/a, from the n-mosfet current to the csa output. when the csa output reaches 0.8v, (which is equivalent to 2a for the switch current) the ocp comparator is tripped to turn off the p-mosfet immediately. short-circuit protection a short-circuit protection scp comparator monitors the vfb pin voltage for output short-circuit protection. when the vfb is lower than 0.2v, the scp comparator forces the pwm oscillator frequency to drop to 1/3 of the normal operation value. this comparator is effective during start-up or an output short-circuit event. rsi/por function when powering up, the open-collector power-on-reset output holds low for about 200ms after vo reaches the preset voltage. when the active-hi reset signal rsi is issued, por goes to low immediately and holds for the figure 31. pwm operation waveforms v eamp v csa1 duty cycle i l v out duty cycle figure 32. skip mode operation waveforms clock i l v out nominal + 1.5% nominal current limit load current 0 8 cycles current limit load current nominal +1.5% 8 cycles nominal clock ISL8009
11 fn6441.0 july 11, 2007 same period of time after rsi comes back to low. the output voltage is unaffected. (please refer to figure 33). when the function is not used, connect rsi to ground and leave the pull-up resistor, r4, open at the por pin. the por output also serves as a 200ms delayed power good signal when the pull-up resistor, r 4, is installed. the rsi pin needs to be directly (or indirectly through resistor, r 5 ) connected to ground for this to function properly. uvlo when the input voltage is below the under-voltage lock out (uvlo) threshold, the regulator is disabled. soft-start-up the soft start-up eliminates the in-rush current during the start-up. the soft-start block outputs a ramp reference to both the voltage loop and the current loop. the two ramps limit the inductor current rising speed as well as the output voltage speed so that the output voltage rises in a controlled fashion. at the very beginning of the start-up, the output voltage is less than 0.2v; hence the pwm operating frequency is 1/3 of the normal frequency. power mosfets the power mosfets are optimized for best efficiency. the on-resistance for the p-mosfet is typically 120m and the on-resistance for the n-mosfet is typically 110m . duty cycle the ISL8009 features duty cycle operation to maximize the battery life. when the battery voltage drops to a level that the ISL8009 can no longer maintain the regulation at the output, the regulator completely turns on the p-mosfet. the maximum drop out voltage under the duty-cycle operation is the product of the load current and the on-resistance of the p-mosfet. enable the enable (en) input allows the user to control the turning on or off of the regulator for purposes such as power-up sequencing. when the regulator is enabled, there is typically a 600s delay for waking up the bandgap reference, then the soft-start-up begins. when the regulator is disabled, the p-mosfet and the n-mosfet are turned off immediately. the 100 soft discharge resistor from lx to gdn is activated and pulls the output to 0v. thermal shutdown the ISL8009 has built-in thermal protection. when the internal temperature reaches +160c, the regulator is completely shutdown. as the temperature drops to +130c, the ISL8009 resumes operation by stepping through a soft- start-up. applications information output inductor and capacitor selection to consider steady state and transient operation, ISL8009 typically uses a 3.3h output inductor. higher or lower inductor values can be used to optimize the total converter system performance. for example, for higher output voltage 3.3v application, in order to decrease the inductor current ripple and output voltage ripp le, the output inductor value can be increased. the inductor ripple current can be expressed in equation 1: the inductor?s saturation current rating needs be at least larger than the peak current. the ISL8009 protects the typical peak current 2.1a. the saturation current needs be over 2.4a for maximum output current application. ISL8009 uses internal compensation network and the output capacitor value is dependant on the output voltage. the ceramic capacitor is recommended to be x5r or x7r. the recommended minimum output capacitor values are shown in table 1. in table 1, the minimum output capacitor value is given for different output voltages to make sure the whole converter system is stable. input capacitor selection the main functions for the input capacitor are to provide decoupling of the parasitic inductance and to provide filtering function to prevent the switchin g current from flowing back to the battery rail. a 10f, x5r or x7r ceramic capacitor is a good starting point for the input capacitor selection. 200ms min 25ns 200ms por rsi v o figure 33. rsi and por timing diagram table 1. output capacitor value vs v out v out c out l 0.8v 10f 1.0h~2.2h 1.2v 10f 1.2h~2.2h 1.6v 10f 1.8h~2.2h 1.8v 10f 1.8h~3.3h 2.5v 10f 1.8h~3.3h 3.3v 10f 1.8h~4.7h 3.6v 10f 1.8h~4.7h i v o 1 v o v in --------- ? ?? ?? ?? ? lf s ? -------------------------------------- - = (eq. 1) ISL8009
12 fn6441.0 july 11, 2007 output voltage setting resistor selection the resistors r 2 and r 3 shown in figure 29 set the output voltage for the adjustable version. the output voltage can be calculated by equation 2: where the 0.8v is the reference voltage. the voltage divider consists of r 2 and r 3 and increases the quiescent current by vo/(r 2 + r 3 ), so larger resistance is desirable. on the other hand, the vfb pin has leakage current that will cause error in the output voltage setting. the leakage current has a typical value of 0.1a. to minimize the accuracy impact on the output voltage, select the r 3 no larger than 200k . for v o = 0.8v, it is recommended to short r 2 and open r 3 . layout recommendation the layout is a very important converter design step to make sure the designed converter works well. for the ISL8009 buck converter, the power loop is composed of the output inductor l, the output capacitor c out , the lx pin and the gnd pin. it is necessary to make the power loop as small as possible. the heat of the ic is mainly dissipated through the thermal pad. maximizing the copper area connected to the thermal pad is preferable. in addition, a solid ground plane is helpful for emi performance. it is recommended to add 5 vias under the thermal pad connection to the solid ground plane. v o 0.8 1 r 2 r 3 ------ - + ?? ?? ?? ? = (eq. 2) ISL8009
13 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6441.0 july 11, 2007 ISL8009 dual flat no-lead plastic package (dfn) // nx (b) section "c-c" 5 (a1) bottom view a 6 area index c c 0.10 0.08 side view 0.15 2x e a b c 0.15 d top view cb 2x 6 8 area index nx l e2 e2/2 ref. e n (nd-1)xe (datum a) (datum b) 5 0.10 8 7 d2 b a mc n-1 12 plane seating c a a3 nx b d2/2 nx k for even terminal/side terminal tip c l e l c c l8.2x3 8 lead dual flat no-lead plastic package symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a3 0.20 ref - b 0.20 0.25 0.32 5,8 d 2.00 bsc - d2 1.50 1.65 1.75 7,8 e 3.00 bsc - e2 1.65 1.80 1.90 7,8 e 0.50 bsc - k0.20 - - - l 0.30 0.40 0.50 8 n 8 2 nd 4 3 rev. 0 6/04 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd refers to the number of terminals on d. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.25mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are prov ided to assist with pcb land pattern design efforts, see intersil technical brief tb389.

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